Structured Computer Organization

by Andrew S. Tanenbaum

Paperback, 1984

Status

Available

Call number

005.1

Library's review

Indeholder "Preface", "1 Introduction", "1.1 Languages, Levels, and Virtual Machines", "1.2 Contemporary Multilevel Machines", "1.3 Historical Evolution of Multilevel Machines", "1.4 Hardware, Software, and Multilevel Machines", "1.5 Processes", "1.6 Outline of this Book", "2 Computer Systems
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Organization", "2.1 Processors", "2.1.1 Instruction Execution", "2.1.2 Parallel Instruction Execution", "2.1.3 Processor Classification", "2.2 Memory", "2.2.1 Bits", "2.2.2 Memory Addresses", "2.2.3 Metabits", "2.2.4 Secondary Memory", "2.3 Input/output", "2.3.1 I/O devices", "2.3.2 I/O processors", "2.3.3 Character Codes", "2.3.4 Error-Correcting Codes", "2.3.5 Frequency-dependent codes", "2.4 Computer Networks and Distributed Systems", "2.4.1 Long-Haul Networks", "2.4.2 Telecommunication", "2.4.3 Local Networks", "2.4.4 Distributed Systems", "2.5 Summary", "3. The Digital Logic Level", "3.1 Gates and Boolean Algebra", "3.1.1 Gates", "3.1.2 Boolean Algebra", "3.1.3 Implementation of Boolean Functions", "3.1.4 Circuit Equivalence", "3.2 Basic Digital Logic Circuits", "3.2.1 Integrated Circuits", "3.2.2 Conventional Circuits", "3.2.3 Arithmetic Circuits", "3.2.4 Clocks", "3.3 Memory", "3.3.1 Latches", "3.3.2 Flip-Flops and Registers", "3.3.3 Memory Organization", "3.3.4 Memory Properties", "3.4 Microprocessors and Microcomputers", "3.4.1 Microprocessor Chips", "3.4.2 Microcomputer Buses", "3.4.3 The Z80 Microprocessor", "3.4.4 The 68000 Microprocessor", "3.5 Interfacing", "3.5.1 I/O Chips", "3.5.2 Address Decoding", "3.5.3 An Example Microcomputer", "4 The Microprogramming Level", "4.1 Review of the Digital Logic Level", "4.1.1 Registers", "4.1.2 Buses", "4.1.3 Multiplexers and Decoder", "4.1.4 ALUs and Shifters", "4.1.5 Clocks", "4.1.6 Main Memory", "4.1.7 Component Packaging", "4.2 An Example Microarchitecture", "4.2.1 The Data Path", "4.2.2 Microinstructions", "4.2.3 Microinstruction Timing", "4.2.4 Microinstruction Sequencing", "4.3 An Example Macroarchitecture", "4.3.1 Stacks", "4.3.2 The Macroinstruction Set", "4.4 An Example Microprogram", "4.4.1 The Micro Assembly Language", "4.4.2 The Example Microprogram", "4.4.3 Remarks about the Microprogram", "4.4.4 Perspective", "4.5 Design of the Microprogramming Level", "4.5.1 Horizontal versus Vertical Microprogramming", "4.5.2 Nanoprogramming", "4.5.3 Improving Performance", "4.6 The IBM 370/125 microprogramming level", "4.6.1 The IBM 370/125 Microarchitecture", "4.6.2 IBM 3125 Microinstructions", "4.7 The PDP-11/60 Microprogramming level", "4.7.1 The PDP-11/60 Microarchitecture", "4.7.2 The PDP-11/60 Microinstructions", "4.8 Summary", "5 The Conventional Machine Level", "5.1 Examples of the Conventional Machine Level", "5.1.1 IBM System/370", "5.1.2 DEC PDP-11", "5.1.3 Motorola MC68000", "5.1.4 Zilog Z80", "5.2 Instruction Formats", "5.2.1 Design Criteria for Instruction Formats", "5.2.2 Expanding Opcodes", "5.2.3 Examples of Instruction Formats", "5.3 Addressing", "5.3.1 Immediate Addressing", "5.3.2 Direct Addressing", "5.3.3 Register Addressing", "5.3.4 Indirect Addressing", "5.3.5 Indexing", "5.3.6 Base-Register Addressing", "5.3.7 Stack Addressing", "5.3.8 Addressing on the PDP-11 and the 68000", "5.3.9 Discussion of Addressing Modes", "5.4 Instruction Types", "5.4.1 Data Movement Instructions", "5.4.2 Dyadic Operations", "5.4.3 Monadic Operations", "5.4.4 Comparisons and Conditional Jumps", "5.4.5 Procedure Call Instructions", "5.4.6 Loop Control", "5.4.7 Input/Output", "5.5 Flow of Control", "5.5.1 Sequential Flow of Control and Jumps", "5.5.2 Procedures", "5.5.3 Coroutines", "5.5.4 Traps", "5.5.5 Interrupts", "5.6 Summary", "6 The Operating System Machine Level", "6.1 Implementation of the Operating System Machine Level", "6.2 Virtual I/O Instructions", "6.2.1 Sequential Files", "6.2.2 Random Access Files", "6.2.3 Implementation of Virtual I/O Instructions", "6.2.4 Directory Management Instructions", "6.2.5 IBM 370 Virtual I/O", "6.2.6 UNIX Virtual I/O", "6.2.7 CP/M Virtual I/O", "6.3 Virtual Instructions Used in Parallel Processing", "6.3.1 Process Creation", "6.3.2 Race Conditions", "6.3.3 Process Synchronization Using Semaphores", "6.4 Virtual Memory", "6.4.1 Paging", "6.4.2 Implementation of Paging", "6.4.3 Demand Paging and the Working Set Model", "6.4.4 Page Replacement Policy", "6.4.5 Page Size and Fragmentation", "6.4.6 Cache Memory", "6.4.7 Segmentation", "6.4.8 The MULTICS Virtual Memory", "6.4.9 Virtual Memory on the IBM/370", "6.4.10 Virtual Memory on the PDP-11", "6.4.11 Virtual Memory on the 68000", "6.5 Job Control Languages", "6.6 Summary", "7 The Assembly Language Level", "7.1 Introduction to Assembly Language", "7.1.1 What Is an Assembly Language?", "7.1.2 Format of an Assembly Language Statement", "7.1.3 Comparion of Assembly Languageand Problem-Oriented Languages", "7.1.4 Program Tuning", "7.2 The Assembly Process", "7.2.1 Two-Pass Assemblers", "7.2.2 Pass One", "7.2.3 Pass Two", "7.2.4 Symbol Table", "7.3 Macros", "7.3.1 Macro Definition, Call and Expansion", "7.3.2 Macros with Parameters", "7.3.3 Implementation of a Macro Facility in an Assembler", "7.4 Linking and Loading", "7.4.1 Tasks performed by the Linker", "7.4.2 Structure of an Object Module", "7.4.3 Binding Time and Dynamic Relocation", "7.4.4 Dynamic Linking", "7.5 Summary", "8 Multilevel Machines", "8.1 Methods of Implementing New Levels", "8.1.1 Interpretation", "8.1.2 Translation", "8.1.3 Procedural Extension", "8.2 Design Strategies for Multilevel Machines", "8.2.1 Top-down design", "8.2.2 Bottom-up design", "8.2.3 Middle-out design", "8.3 Program Portability", "8.3.1 A Universal Programming Language", "8.3.2 The Brute Force Approach", "8.3.3 UNCOL", "8.3.4 Abstract Machine Language", "8.3.5 Portable Compilers", "8.3.6 Emulation", "8.4 Self-Virtualizing Machines", "8.4.1 IBM VM/370 system", "8.4.2 Goals of self-virtualizing machines", "8.4.3 Implementation of a self-virtualizing machine", "8.5 The Compiler-Interpreter Interface", "8.5.1 High-Level Interfaces", "8.5.2 Discussion of High-Level Interfaces", "8.6 Summary", "9. Reading List and Bibliography", "9.1 Suggestions for Further Reading", "9.1.1 Introduction and General Works", "9.1.2 Computer Systems Organization", "9.1.3 The Digital Logic Level", "9.1.4 The Microprogramming Level", "9.1.5 The Conventional Machine Level", "9.1.6 The Operating System Machine Level", "9.1.7 The Assembly Language Level", "9.1.8 Multilevel computers", "9.1.9 Binary Numbers and Arithmetic", "9.2 Alphabetical Bibliography", "Appendix A Binary Numbers", "A.1 Finite Precision Numbers", "A.2 Radix Number Systems", "A.3 Conversion from One Radix to Another", "A.4 Negative Binary Numbers", "A.5 Binary Arithmetic", "Appendix B Floating-point Number", "Index".

Glimrende gennemgang af hvordan man designer computere fra transistorer og op til højniveausprog og virtuelle maskiner.
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Publication

Prentice-Hall (1984), Paperback, 480 pages

Description

This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum's renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author's popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. A CD-ROM for assembly language programmers is available for teachers. For all computer professionals and engineers who need an overview or introduction to computer architecture.

Language

Original language

English

Physical description

587 p.; 23.3 cm

ISBN

0138546053 / 9780138546052

Local notes

Omslag: Ikke angivet
Omslaget viser titel, forfatternavn og forlaget med hvid skrift på rød baggrund og ordene Second Edition
Indskannet omslag - N650U - 150 dpi
Dette eksemplar tilhører Marianne Søby

Pages

587

Library's rating

Rating

½ (35 ratings; 4)

DDC/MDS

005.1
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